Timing analysis of circuits using sub-circuit timing models

Abstract

Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.