The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Jul. 23, 2012
Applicants:

Wojciech Jakub Poppe, San Jose, CA (US);

Puneet Gupta, San Jose, CA (US);

Ilyas Elkin, Sunnyvale, CA (US);

Inventors:

Wojciech Jakub Poppe, San Jose, CA (US);

Puneet Gupta, San Jose, CA (US);

Ilyas Elkin, Sunnyvale, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/03 (2006.01); G01R 31/317 (2006.01); H01L 21/66 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0315 (2013.01); G01R 31/31725 (2013.01); H01L 22/34 (2013.01); G01R 31/2831 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.


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