The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Dec. 03, 2013
Applicant:

Denso Corporation, Kariya, Aichi-pref., JP;

Inventors:

Kouji Eguchi, Kariya, JP;

Youhei Oda, Okazaki, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/06 (2013.01); H01L 21/26513 (2013.01); H01L 21/306 (2013.01); H01L 21/308 (2013.01); H01L 21/30625 (2013.01); H01L 29/0615 (2013.01); H01L 29/0634 (2013.01); H01L 29/0692 (2013.01); H01L 29/66 (2013.01); H01L 29/66712 (2013.01); H01L 29/66734 (2013.01); H01L 29/7802 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 29/063 (2013.01); H01L 29/1095 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate.


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