The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Dec. 07, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Nathan C. Buck, Underhill, VT (US);

Eric A. Foreman, Fairfax, VT (US);

Jeffrey G. Hemmett, St. George, VT (US);

Kerim Kalafala, Rhinebeck, NY (US);

Gregory M. Schaeffer, Poughkeepsie, NY (US);

Stephen G. Shuma, Underhill, VT (US);

Natesan Venkateswaran, Hopewell Junction, NY (US);

Chandramouli Visweswariah, Croton-on-Hudson, NY (US);

Michael H. Wood, Hopewell Junction, NY (US);

Vladimir Zolotov, Putnam Valley, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/5081 (2013.01);
Abstract

A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.


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