The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2016
Filed:
Apr. 03, 2014
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Cheng-Chung Lin, Hsinchu, TW;
Ming-Zhang Kuo, Qionglin Township, TW;
Sang Hoo Dhong, Hsin-Chu, TW;
Ho-Chieh Hsieh, Hsinchu, TW;
Kuo Feng Tseng, Taipei, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Abstract
One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.