The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

May. 30, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Hongbo Rong, San Jose, CA (US);

Cheng Wang, San Ramon, CA (US);

Hyunchul Park, Santa Clara, CA (US);

Youfeng Wu, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 9/46 (2006.01); G06F 9/30 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3838 (2013.01); G06F 9/3017 (2013.01); G06F 9/30127 (2013.01); G06F 9/384 (2013.01); G06F 9/3834 (2013.01); G06F 8/434 (2013.01); G06F 8/441 (2013.01); G06F 8/443 (2013.01);
Abstract

In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.


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