The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Nov. 18, 2015
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventor:

Chi-Yi Shao, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H04L 29/06 (2006.01); H02M 3/07 (2006.01); H03K 3/012 (2006.01); H03K 5/159 (2006.01); H03K 17/687 (2006.01); G11C 5/14 (2006.01); H03K 5/151 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H04L 63/0457 (2013.01); G11C 5/145 (2013.01); G11C 5/147 (2013.01); H02M 3/07 (2013.01); H02M 3/073 (2013.01); H03K 3/012 (2013.01); H03K 5/159 (2013.01); H03K 5/1515 (2013.01); H03K 17/687 (2013.01); H04L 63/0861 (2013.01); H02M 2003/075 (2013.01); H03K 2005/00019 (2013.01);
Abstract

The invention provides a memory apparatus, a charge pump circuit, and a voltage pumping method thereof. The charge pump circuit including a plurality of delay units, a latch circuit, and a plurality of charge pump units. The delay units respectively generate a plurality clock signals according to an output clock signal. The latch circuit receive a final stage clock signal of the clock signals and a latch enable signal. The latch circuit decides whether to latch final stage clock signal or not to generate the output clock signal according to the latch enable signal. The first stage of the charge pump unit receives an input voltage, and the charge pump units operate a voltage pumping operation on the input voltage to generate an output voltage according to the clock signals and the output clock signal.


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