The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

May. 09, 2012
Applicants:

Hon Shing Lau, Dorado Hills, CA (US);

Scott Siers, Elk Grove, CA (US);

Ruchira Liyanage, Folsom, CA (US);

Inventors:

Hon Shing Lau, Dorado Hills, CA (US);

Scott Siers, Elk Grove, CA (US);

Ruchira Liyanage, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/096 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0016 (2013.01);
Abstract

In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.


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