The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Jul. 03, 2014
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Andrea Redaelli, Casatenovo, IT;
Cinzia Perrone, Bellusco, IT;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 45/00 (2006.01); H01L 23/525 (2006.01); H01L 27/24 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1253 (2013.01); H01L 23/481 (2013.01); H01L 23/5256 (2013.01); H01L 27/2463 (2013.01); H01L 27/2472 (2013.01); H01L 45/06 (2013.01); H01L 45/126 (2013.01); H01L 45/144 (2013.01); H01L 2924/0002 (2013.01);
Abstract
Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.