The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Jan. 04, 2011
Applicants:
Carlos Mazure, Bernin, FR;
Richard Ferrant, Esquibien, FR;
Inventors:
Carlos Mazure, Bernin, FR;
Richard Ferrant, Esquibien, FR;
Assignee:
Soitec, Bernin, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01); H01L 21/8222 (2006.01); H01L 27/12 (2006.01); H01L 21/74 (2006.01); H01L 21/84 (2006.01); H01L 27/108 (2006.01); H01L 29/732 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/743 (2013.01); H01L 21/84 (2013.01); H01L 27/10802 (2013.01); H01L 29/732 (2013.01); H01L 27/10873 (2013.01); H01L 29/7841 (2013.01); H01L 29/78639 (2013.01);
Abstract
The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.