The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Dec. 11, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Joseph Ervin, Wappingers Falls, NY (US);

Juntao Li, Cohoes, NY (US);

Chengwen Pei, Danbury, CT (US);

Geng Wang, Stormville, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 23/00 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 23/564 (2013.01); H01L 21/76229 (2013.01); H01L 29/0646 (2013.01); H01L 29/0649 (2013.01);
Abstract

A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.


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