The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Nov. 02, 2010
Applicants:
Zoltan Ring, Chapel Hill, NC (US);
Scott Thomas Sheppard, Chapel Hill, NC (US);
Helmut Hagleitner, Zebulon, NC (US);
Inventors:
Zoltan Ring, Chapel Hill, NC (US);
Scott Thomas Sheppard, Chapel Hill, NC (US);
Helmut Hagleitner, Zebulon, NC (US);
Assignee:
Cree, Inc., Durham, NC (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/12 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/778 (2006.01); H01L 29/812 (2006.01); H01L 21/445 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 29/4175 (2013.01); H01L 29/7787 (2013.01); H01L 29/812 (2013.01); H01L 21/445 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01); H01L 29/452 (2013.01);
Abstract
A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.