The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Dec. 08, 2014
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Jung Ryul Ahn, Namyangju-si, KR;

Jum Soo Kim, Yongin-si, KR;

Assignee:

SK HYNIX INC., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 2211/5641 (2013.01); G11C 2211/5648 (2013.01);
Abstract

A semiconductor memory device, a memory system having the same, and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory cells electrically coupled between a source select transistor and a drain select transistor, a peripheral circuit configured to perform a program operation on the plurality of memory cells, and a control logic unit configured to control the operation of the peripheral circuit so that at least two memory cells of the plurality of memory cells adjacent to the source select transistor and at least two memory cells of the plurality of memory cells adjacent to the drain select transistor are programmed to have a relatively fewer number of data bits than that of remaining memory cells of the plurality of memory cells in the program operation.


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