The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Dec. 12, 2014
Synopsys, Inc., Mountain View, CA (US);
Ajit Sequeira, Bangalore, IN;
Subramanyam Sripada, Hillsboro, OR (US);
Subrahmanya Narasimha Murthy Palla, Hyderabad, IN;
Synopsys, Inc., Mountain View, CA (US);
Abstract
A mode of a circuit design is simplified by eliminating clocks and corresponding timing exceptions and timing constraints from the mode. A system receives a description of a mode of a circuit. The system identifies sets of clock pairs and corresponding timing exceptions associated with timing nodes of the mode, each clock pair comprising a launch clock and a capture clock. The system compares time intervals between an edge of the launch clock and a corresponding edge of the capture clock for the clock pairs subject to timing exceptions associated with the timing path. The system identifies certain clock pairs as critical based on a comparison of the time interval associated with each clock pair. The system simplifies the mode by eliminating non-critical clocks and corresponding timing exceptions. The modified mode is used for performing timing analysis.