The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

May. 22, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Wilfried E. Haensch, Somers, NY (US);

Bahman Hekmatshoar-Tabari, White Plains, NY (US);

Ali Khakifirooz, Mountain View, CA (US);

Tak H. Ning, Yorktown Heights, NY (US);

Ghavam G. Shahidi, Pound Ridge, NY (US);

Davood Shahrjerdi, White Plains, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 21/265 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 21/0262 (2013.01); H01L 21/02639 (2013.01); H01L 21/2257 (2013.01); H01L 21/265 (2013.01); H01L 21/823814 (2013.01); H01L 21/84 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/41783 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/7834 (2013.01); H01L 29/7841 (2013.01); H01L 29/78618 (2013.01); H01L 29/78621 (2013.01);
Abstract

A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.


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