The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2016
Filed:
Aug. 01, 2014
Applicant:
Empire Technology Development Llc, Wilmington, DE (US);
Inventor:
Zhijiong Luo, Poughkeepsie, NY (US);
Assignee:
EMPIRE TECHNOLOGY DEVELOPMENT LLC, Wilmington, DE (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/768 (2006.01); H01L 21/3065 (2006.01); H01L 23/367 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/3065 (2013.01); H01L 21/76898 (2013.01); H01L 23/367 (2013.01); H01L 25/50 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01);
Abstract
Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled.