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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9484276 B1

PDFFull Text
Date of Patent:
Nov. 01, 2016

Filed:

Feb. 12, 2015

Semiconductor mounting device and method for manufacturing semiconductor mounting device

Applicant:

Ibiden Co., Ltd., Ogaki, JP;

Inventors:

Hiroyuki Watanabe, Ogaki, JP;

Masahiro Kaneko, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki-shi, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Mohsen Ahmadi

Assistant Examiner:

Gustavo Ramallo

Int. Cl.
CPC ...
H01L 23/13 (2006.01); H01L 23/12 (2006.01); H01L 23/498 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 21/486 (2013.01); H01L 21/76898 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 23/3128 (2013.01); H01L 2224/11005 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor mounting device including a first substrate having insulation layers, conductor layers formed on the insulation layers, and via conductors connecting the conductor layers, a second substrate having insulation layers and conductor layers formed on the insulation layers of the second substrate, first bumps connecting the first substrate and the second substrate and formed on an outermost conductor layer of the first substrate formed on an outermost insulation layer of the first substrate, and second bumps positioned to mount a semiconductor element to the second substrate and formed on an outermost conductor layer of the second substrate formed on an outermost insulation layer of the second substrate. The second substrate has a thickness which is greater than a thickness of the first substrate.

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