The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2016
Filed:
May. 13, 2015
Nvidia Corporation, Santa Clara, CA (US);
Stephen Felix, Bristol, GB;
Hwong-Kwo Lin, Palo Alto, CA (US);
Spencer Gold, Pepperell, MA (US);
Jing Guo, Shanghai, CN;
Andreas Gotterba, Santa Clara, CA (US);
Jason Golbus, Palo Alto, CA (US);
Karthik Natarajan, San Jose, CA (US);
Jun Yang, Shanghai, CN;
Zhenye Jiang, San Jose, CA (US);
Ge Yang, Dublin, CA (US);
Lei Wang, San Jose, CA (US);
Yong Li, Shanghai, CN;
Hua Chen, Shanghai, CN;
Haiyan Gong, San Jose, CA (US);
Beibei Ren, Fremont, CA (US);
Eric Voelkel, Ben Lomond, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.