The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

Jul. 30, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ching-Hao Shaw, San Jose, CA (US);

Subramani Kengeri, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/52 (2006.01); G11C 5/00 (2006.01); G11C 11/412 (2006.01); H01L 23/522 (2006.01); H01L 27/10 (2006.01); H01L 27/105 (2006.01); H01L 49/02 (2006.01); G11C 11/417 (2006.01); H01L 23/556 (2006.01); H01L 27/06 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 5/005 (2013.01); G11C 11/417 (2013.01); G11C 11/4125 (2013.01); G11C 29/52 (2013.01); H01L 23/5223 (2013.01); H01L 23/556 (2013.01); H01L 27/0629 (2013.01); H01L 27/101 (2013.01); H01L 27/105 (2013.01); H01L 27/1104 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 2924/0002 (2013.01); Y10T 29/43 (2015.01);
Abstract

A circuit includes a capacitor and a memory element. The capacitor includes a first conductive layer, a first terminal, and a second terminal. The first conductive layer includes a first plurality of bars extending along a first direction and parallel to one another, where two adjacent bars of the first plurality of bars have a first capacitance therebetween. The first terminal is coupled with a first bar of the two adjacent bars, and the second terminal is coupled with a second bar of the two adjacent bars. The memory element has an input coupled with the first terminal and an output coupled with the second terminal. The capacitor is configured to inhibit changing a logic state at the input of the memory element.


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