The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2016
Filed:
Mar. 11, 2015
Qualcomm Incorporated, San Diego, CA (US);
Mamta Bansal, San Diego, CA (US);
Uday Doddannagari, San Diego, CA (US);
Paras Gupta, San Diego, CA (US);
Ramaprasath Vilangudipitchai, San Diego, CA (US);
Parissa Najdesamii, San Diego, CA (US);
Dorav Kumar, San Diego, CA (US);
Nitin Partani, Bangalore KRN, IN;
QUALCOMM INCORPORATED, San Diego, CA (US);
Abstract
A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.