The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

May. 13, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yun He, Santa Clara, CA (US);

Sanjib Sarkar, Folsom, CA (US);

Fei Deng, Folsom, CA (US);

Senthil Arun Singaravelu, Folsom, CA (US);

Narender Nagulapally, Folsom, OR (US);

Pranali Shah, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H04L 7/00 (2006.01); G06F 13/40 (2006.01); H04L 7/033 (2006.01); H04L 7/027 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); G06F 13/4072 (2013.01); H04L 7/0062 (2013.01); H04L 7/0079 (2013.01); H04L 7/0276 (2013.01); H04L 7/0332 (2013.01); H04L 25/03949 (2013.01); H04L 7/0087 (2013.01);
Abstract

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.


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