The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
May. 28, 2010
Applicant:
Jeffrey Junhao Xu, Jhubei, TW;
Inventor:
Jeffrey Junhao Xu, Jhubei, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6659 (2013.01); H01L 21/02315 (2013.01); H01L 21/28194 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/7833 (2013.01); H01L 21/02052 (2013.01); H01L 21/306 (2013.01); H01L 29/665 (2013.01);
Abstract
An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer.