The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Sep. 23, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

James W. Adkisson, Jericho, VT (US);

Brent A. Anderson, Jericho, VT (US);

Andres Bryant, Burlington, VT (US);

Edward J. Nowak, Essex Junction, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/36 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1041 (2013.01); H01L 21/28026 (2013.01); H01L 29/0847 (2013.01); H01L 29/1045 (2013.01); H01L 29/36 (2013.01); H01L 29/6659 (2013.01); H01L 29/66537 (2013.01); H01L 29/66583 (2013.01); H01L 29/78 (2013.01); H01L 21/2652 (2013.01); H01L 21/26586 (2013.01);
Abstract

A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.


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