The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
May. 28, 2014
James W. Miller, Austin, TX (US);
Melanie Etherton, Austin, TX (US);
Alex P. Gerdemann, Austin, TX (US);
Mohamed S. Moosa, Austin, TX (US);
Jonathan M. Phillippe, Austin, TX (US);
Robert S. Ruth, Austin, TX (US);
James W. Miller, Austin, TX (US);
Melanie Etherton, Austin, TX (US);
Alex P. Gerdemann, Austin, TX (US);
Mohamed S. Moosa, Austin, TX (US);
Jonathan M. Phillippe, Austin, TX (US);
Robert S. Ruth, Austin, TX (US);
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.