The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Oct. 08, 2014
Industrial Technology Research Institute, Hsinchu, TW;
Chung Yuan Christian University, Taoyuan County, TW;
National Tsing Hua University, Hsinchu, TW;
Yow-Tyng Nieh, Hsinchu County, TW;
Shih-Hsu Huang, Hsinchu County, TW;
Shih-Chieh Chang, Hsinchu, TW;
Chung-Han Chou, New Taipei, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Chung Yuan Christian University, Chung-Li, TW;
National Tsing Hua University, Hsinchu, TW;
Abstract
A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.