The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Dec. 22, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Efraim Rotem, Haifa, IL;

Nir Rosenzweig, Givat Ella, IL;

Doron Rajwan, Rishon Le-Zion, IL;

Nadav Shulman, Tel Mond, IL;

Gal Leibovich, Kiryat Yam, IL;

Tomer Ziv, Rishon Lezion, IL;

Amit Gabai, Kiryat Biyalik, IL;

Jorge P. Rodriguez, Portland, OR (US);

Jeffrey A. Carlson, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G05F 1/10 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
G05F 1/10 (2013.01); G06F 1/324 (2013.01); H03L 7/08 (2013.01);
Abstract

A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.


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