The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Mar. 14, 2014
Johnstech International Corporation, Minneapolis, MN (US);
David Johnson, Wayzata, MN (US);
Jeffrey Sherry, Savage, MN (US);
Harlan Faller, St. Anthony, MN (US);
Brian Warwick, Ben Lomond, CA (US);
Sarosh Patel, Sunnyvale, MN (US);
John Bucher, Corcoran, MN (US);
Jay Drescher, Marine on St. Croix, MN (US);
Johnstech International Corporation, Minneapolis, MN (US);
Abstract
The IC test system provides a system and method for thermal management of test pins. A test pin array () in a pin guide () is mounted in a retainer () which is located between an IC wafer () which contains IC devices to be tested (DUT) and a load board () which provides pathways to test signals to the DUT. On the other side of the load board is a contact plate () which together with the retainer straddles the load board. Leg extensions () pass through the load board apertures () and provide a thermal circuit from the contact plate to the retainer and to the pin array. On the upper side of the contact plate is a cooling/heating system with a thermal electric peltier device () and a further heat exchanger () as needed. Holes () are provided in the legs () to provide a supply of dry air to the wafer and pin array to minimize condensation as a result of cooling effects.