The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jan. 31, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Chia-Hui Chen, Hsinchu, TW;

Wei Yu Ma, Taitung, TW;

Kuo-Ji Chen, Wu-Ku, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 23/522 (2006.01); H01L 23/60 (2006.01); H01L 25/065 (2006.01); H01L 27/092 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 23/5226 (2013.01); H01L 23/60 (2013.01); H01L 25/0657 (2013.01); H01L 27/0251 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 23/481 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/0002 (2013.01);
Abstract

One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.


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