The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jan. 04, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Ruei Lin, Taipei, TW;

Yen-Ming Peng, Taoyuan County, TW;

Han-Wei Yang, Hsinchu, TW;

Chen-Chung Lai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/76801 (2013.01); H01L 21/76808 (2013.01); H01L 21/76822 (2013.01); H01L 21/76877 (2013.01); H01L 23/3178 (2013.01); H01L 23/481 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.


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