The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jul. 27, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yuan-Chih Hsieh, Hsinchu, TW;

Li-Cheng Chu, Taipei, TW;

Ming-Tung Wu, Hsinchu, TW;

Ping-Yin Liu, Yonghe, TW;

Lan-Lin Chao, Sindian, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/7684 (2013.01); H01L 21/7685 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.


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