The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jul. 14, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ya-Ling Lee, Hsinchu, TW;

Wen-Cheng Yang, Hsinchu, TW;

Victor Y. Lu, Foster City, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53209 (2013.01); H01L 21/76843 (2013.01); H01L 21/76867 (2013.01); H01L 21/76873 (2013.01); H01L 21/76879 (2013.01); H01L 21/76883 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01);
Abstract

Some embodiments relate to a method of manufacturing an integrated circuit device. In this method a dielectric layer is formed over a substrate. The dielectric layer comprises an opening arranged within the dielectric layer. A first cobalt liner is formed along bottom and sidewall surfaces of the opening. A barrier liner is formed on exposed surfaces of the first cobalt liner. A bulk cobalt layer is formed in the opening and over the barrier liner to fill a remaining space of the opening.


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