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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9472436 B1

PDFFull Text
Date of Patent:
Oct. 18, 2016

Filed:

May. 08, 2014

Multiple bonding layers for thin-wafer handling

Applicant:

Brewer Science Inc., Rolla, MO (US);

Inventors:

Rama Puligadda, Rolla, MO (US);

Xing-Fu Zhong, Rolla, MO (US);

Tony D. Flaim, St. James, MO (US);

Jeremy McCutcheon, Rolla, MO (US);

Assignee:

Brewer Science Inc., Rolla, MO (US);

Attorney:

Hovey Williams LLP

Primary Examiner:

Laura Menz

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/683 (2006.01); H01L 21/20 (2006.01); H01L 23/00 (2006.01); B32B 38/00 (2006.01); B32B 38/10 (2006.01); B32B 43/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); B32B 38/0008 (2013.01); B32B 38/10 (2013.01); B32B 43/006 (2013.01); H01L 21/2007 (2013.01); H01L 21/6836 (2013.01); H01L 24/83 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/351 (2013.01); Y10T 156/10 (2015.01); Y10T 156/11 (2015.01); Y10T 156/1126 (2015.01); Y10T 428/24942 (2015.01); Y10T 428/26 (2015.01); Y10T 428/31511 (2015.04); Y10T 428/31551 (2015.04); Y10T 428/31663 (2015.04); Y10T 428/31721 (2015.04); Y10T 428/31725 (2015.04); Y10T 428/31935 (2015.04); Y10T 428/31938 (2015.04);
Abstract

Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

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