The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jul. 20, 2015
Applicant:

Sandisk 3d Llc, Milpitas, CA (US);

Inventors:

Abhijit Bandyopadhyay, San Jose, CA (US);

Tanmay Kumar, Pleasanton, CA (US);

Scott Brad Herner, San Jose, CA (US);

Christopher J. Petti, Mountain View, CA (US);

Roy E. Scheuerlein, Cupertino, CA (US);

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 11/56 (2006.01); H01L 27/112 (2006.01); H01L 27/102 (2006.01); H01L 45/00 (2006.01); H01L 29/861 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 17/165 (2013.01); G11C 11/5692 (2013.01); G11C 17/18 (2013.01); H01L 27/1021 (2013.01); H01L 27/11206 (2013.01); H01L 27/2409 (2013.01); H01L 27/2418 (2013.01); H01L 27/2481 (2013.01); H01L 29/8615 (2013.01); H01L 45/04 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/1675 (2013.01);
Abstract

A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.


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