The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jun. 25, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alexander Gendler, Kiriat Motzkin, IL;

Efraim Rotem, Haifa, IL;

Julius Mandelblat, Haifa, IL;

Alexander Lyakhov, Haifa, IL;

Larisa Novakovsky, Haifa, IL;

George Leifman, Haifa, IL;

Lev Makovsky, Haifa, IL;

Ariel Sabba, Karmiel, IL;

Niv Tokman, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/04 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/04 (2013.01); G06F 1/32 (2013.01);
Abstract

In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.


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