The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Dec. 31, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seung-Hyun Song, Hwaseong-si, KR;

Nak-Jin Son, Suwon-si, KR;

Kwang-Seok Lee, Osan-si, KR;

Chang-Wook Jeong, Hwaseong-si, KR;

Ui-Hui Kwon, Hwaseong-si, KR;

Dong-Won Kim, Seongnam-si, KR;

Young-Kwan Park, Incheon, KR;

Keun-Ho Lee, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66803 (2013.01); H01L 21/26586 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 29/6681 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01);
Abstract

Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.


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