The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Dec. 31, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung Ho Kim, Suwon-si, KR;

Daehyun Jang, Seongnam-si, KR;

Myoungbum Lee, Seoul, KR;

Kihyun Hwang, Seongnam-si, KR;

Sangryol Yang, Hwaseong-si, KR;

Yong-Hoon Son, Yongin-si, KR;

Ju-Eun Kim, Seoul, KR;

Sunghae Lee, Suwon-si, KR;

Dongwoo Kim, Incheon, KR;

JinGyun Kim, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02675 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 27/11551 (2013.01); H01L 27/11578 (2013.01); H01L 29/7926 (2013.01);
Abstract

Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.


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