The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2016
Filed:
Dec. 29, 2015
Dae-ho Lee, Hwaseong-si, KR;
Hyo-soon Kang, Seoul, KR;
Seok-hong Kwon, Hwaseong-si, KR;
Tae-young Yoon, Hwaseong-si, KR;
Hee-jin Lee, Seongnam-si, KR;
Dae-Ho Lee, Hwaseong-si, KR;
Hyo-Soon Kang, Seoul, KR;
Seok-Hong Kwon, Hwaseong-si, KR;
Tae-Young Yoon, Hwaseong-si, KR;
Hee-Jin Lee, Seongnam-si, KR;
Abstract
A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.