The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Oct. 13, 2015
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wei-Chen Chang, Kaohsiung, TW;

Wen-Hao Ching, Hsinchu County, TW;

Chih-Hsin Chen, Changhua County, TW;

Shih-Chen Wang, Taipei, TW;

Ching-Sung Yang, Hsinchu, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 17/18 (2006.01); G11C 16/14 (2006.01); G11C 17/16 (2006.01); H01L 27/115 (2006.01); H01L 29/10 (2006.01); H01L 23/525 (2006.01); H01L 27/108 (2006.01); H01L 27/11 (2006.01); H01L 27/112 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01); H01L 29/868 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 16/0408 (2013.01); G11C 16/14 (2013.01); G11C 17/16 (2013.01); H01L 23/5256 (2013.01); H01L 27/10897 (2013.01); H01L 27/1116 (2013.01); H01L 27/1156 (2013.01); H01L 27/11206 (2013.01); H01L 27/11524 (2013.01); H01L 29/0649 (2013.01); H01L 29/1033 (2013.01); H01L 29/78 (2013.01); H01L 29/868 (2013.01); H01L 29/8611 (2013.01); G11C 29/785 (2013.01);
Abstract

A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.


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