The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Dec. 06, 2013
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

Brian S. Leibowitz, San Francisco, CA (US);

Pradeep Batra, Santa Clara, CA (US);

Trung Am Diep, San Jose, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/85 (2013.01); G06F 21/78 (2013.01); G09C 1/00 (2006.01); H04L 9/06 (2006.01); H04L 9/12 (2006.01);
U.S. Cl.
CPC ...
G06F 21/85 (2013.01); G06F 21/78 (2013.01); G09C 1/00 (2013.01); H04L 9/065 (2013.01); H04L 9/12 (2013.01); G06F 2221/2107 (2013.01); H04L 2209/12 (2013.01); H04L 2209/56 (2013.01);
Abstract

Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.


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