The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2016
Filed:
Jul. 06, 2015
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Ming Cai, San Diego, CA (US);
Samit Sengupta, San Diego, CA (US);
Chock Hing Gan, San Diego, CA (US);
PR Chidambaram, San Diego, CA (US);
Assignee:
Qualcomm Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); H01L 27/00 (2006.01); H01L 29/00 (2006.01); G06F 17/50 (2006.01); H01L 27/088 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); G06F 17/5068 (2013.01); H01L 21/28035 (2013.01); H01L 21/823456 (2013.01); H01L 22/14 (2013.01); H01L 22/20 (2013.01); H01L 27/0207 (2013.01); H01L 29/4916 (2013.01);
Abstract
A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.