The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Dec. 19, 2013
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Derek W. Robinson, Tucson, AZ (US);

Amitava Chatterjee, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 21/8249 (2006.01); H01L 29/66 (2006.01); H01L 29/732 (2006.01); H01L 29/10 (2006.01); H01L 21/761 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0623 (2013.01); H01L 21/761 (2013.01); H01L 21/76229 (2013.01); H01L 21/8249 (2013.01); H01L 29/1004 (2013.01); H01L 29/66272 (2013.01); H01L 29/732 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01);
Abstract

A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.


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