The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9460814 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 04, 2016

Filed:

May. 02, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joshua M. Dragula, Pleasant Valley, NY (US);

Charles J. Montrose, Clintondale, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G11C 29/44 (2006.01); G11C 29/56 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 29/56008 (2013.01); G11C 29/38 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01);
Abstract

A method of determining multi-bit upsets (MBU) during soft error rate (SER) testing of a memory device under test is provided. The method may include receiving an error indication based on a comparison between a generated test data pattern written to an address location on the memory device and a stored version of the generated test data pattern read from the address location on the memory device. The error indication is associated with error information associated with the comparison between the generated test data and the stored version of the generated test data. Based on the received error indication, a count value associated with one of a predetermined number of passes a plurality of generated test data patterns traverse between a first and a second memory address location on the memory device is determined. The MBU is determined based on the address location, the error information, and the count value.


Find Patent Forward Citations

Dragula, Joshua. (2016). Memory tester design for soft error rate (ser) failure analysis (U.S. Patent No. 9460814). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9460814

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