The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Jan. 27, 2015
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventors:

Chih-Chun Chen, Taipei, TW;

Chun-Hung Lin, Hsinchu, TW;

Cheng-Da Huang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/14 (2006.01); H01L 27/115 (2006.01); G11C 5/06 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); G11C 16/08 (2006.01); H01L 27/092 (2006.01); H02M 1/14 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01); H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 5/063 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); H01L 27/092 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 29/0642 (2013.01); H01L 29/1095 (2013.01); H02M 1/14 (2013.01); G11C 16/26 (2013.01); H02M 3/07 (2013.01);
Abstract

The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a substrate, first to three wells and first to three transistors. The first to three wells are disposed in the substrate, and the first to three transistors are respectively forming on the first to three wells. The first to third transistors are coupled in series. Wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal. Moreover, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.


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