The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2016
Filed:
Jul. 30, 2012
Jose Emmanuel Schutt-aine, Urbana, IL (US);
Dennis Nagle, Peabody, MA (US);
Feras Al-hawari, Chelmsford, MA (US);
Ambrish Kant Varma, Nashua, NH (US);
Jilin Tan, Nashua, NH (US);
Ping Liu, Shanghai, CN;
Shangli Wu, New Providence, NJ (US);
Yubao Meng, Shanghai, CN;
Qi Zhao, Shanghai, CN;
Zhongyong Zhou, Shanghai, CN;
Jose Emmanuel Schutt-Aine, Urbana, IL (US);
Dennis Nagle, Peabody, MA (US);
Feras Al-Hawari, Chelmsford, MA (US);
Ambrish Kant Varma, Nashua, NH (US);
Jilin Tan, Nashua, NH (US);
Ping Liu, Shanghai, CN;
Shangli Wu, New Providence, NJ (US);
Yubao Meng, Shanghai, CN;
Qi Zhao, Shanghai, CN;
Zhongyong Zhou, Shanghai, CN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.