The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2016
Filed:
Jun. 21, 2012
Yu Cao, Saratoga, CA (US);
Jun YE, Palo Alto, CA (US);
Venugopal Vellanki, San Jose, CA (US);
Johannes Catharinus Hubertus Mulkens, Valkenswaard, NL;
Yu Cao, Saratoga, CA (US);
Jun Ye, Palo Alto, CA (US);
Venugopal Vellanki, San Jose, CA (US);
Johannes Catharinus Hubertus Mulkens, Valkenswaard, NL;
ASML NETHERLANDS B.V., Veldhoven, NL;
Abstract
The present invention discloses various system and process embodiments where wafer-metrology and direct measurements of the lithography apparatus characteristics are combined to achieve temporal drift reduction in a lithography apparatus/process using a simulation model. The simulation model may have sub-components. For example, a sub-model may represent a first set of optical conditions, and another sub-model may represent a second set of optical conditions. The first set of optical conditions may be a standard set of illumination conditions, and the second set may be a custom set of illumination conditions. Using the inter-relationship of the sub-models, stability control under custom illumination condition can be achieved faster without wafer metrology.