The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2016
Filed:
Jan. 28, 2015
Pascal Kamel Abouda, Saint Lys, FR;
Celine Hounaïda Abouda, Saint Lys, FR;
Patrice Besse, Tournfeuille, FR;
Pascal Kamel Abouda, Saint Lys, FR;
Celine Hounaïda Abouda, Saint Lys, FR;
Patrice Besse, Tournfeuille, FR;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuitcomprises in addition to a clock networkan integrated test clock signal generatorto generate test clock signals that are provided via controllable multiplexersto an analog and digital sub-circuitry, respectively, of the mixed-mode integrated circuit. The test clock signals are generated on basis of an input test clock signal having a controllable frequency. The clock network generates clock signals for the sub-circuitries that are used by the sub-circuitries under normal operational conditions. The controllable multiplexers provide either the test clock signal to a specific sub-circuitry or a clock signal received from the clock network.