The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Jun. 05, 2015
Applicant:

Rf Micro Devices, Inc., Greensboro, NC (US);

Inventor:

Andrew P. Ritenour, Colfax, NC (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/47 (2006.01); H01L 29/778 (2006.01); H01L 29/812 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/517 (2013.01); H01L 21/28264 (2013.01); H01L 29/1054 (2013.01); H01L 29/42364 (2013.01); H01L 29/78 (2013.01); H01L 29/2003 (2013.01); H01L 29/475 (2013.01); H01L 29/4958 (2013.01); H01L 29/518 (2013.01); H01L 29/778 (2013.01); H01L 29/812 (2013.01);
Abstract

A Schottky gated transistor having reduced gate leakage current is disclosed. The Schottky gated transistor includes a substrate and a plurality of epitaxial layers disposed on the substrate. Further included is a gate contact having an interfacial layer disposed on a surface of the plurality of epitaxial layers and having a thickness that is between about 5 Angstroms (Å) and 40 Å. The interfacial layer can be made up of non-native materials in contrast to a native insulator such as silicon dioxide (SiO) that is used as an insulating gate layer with silicon-based power transistors. The Schottky gated transistor further includes at least one metal layer disposed over the interfacial layer. A source contact and a drain contact are disposed on the surface of the plurality of epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.


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