The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Sep. 30, 2015
Applicant:
Globalfoundries Inc., Grand Caymay, KY;
Inventors:
Jagar Singh, Clifton Park, NY (US);
Andy Wei, Kanata, CA;
Mahadeva Iyer Natarajan, Clifton Park, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/861 (2006.01); H01L 29/866 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0657 (2013.01); H01L 21/308 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/30604 (2013.01); H01L 27/0251 (2013.01); H01L 27/0255 (2013.01); H01L 27/0259 (2013.01); H01L 27/0296 (2013.01); H01L 29/41708 (2013.01); H01L 29/456 (2013.01); H01L 29/861 (2013.01); H01L 29/866 (2013.01);
Abstract
Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.