The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
May. 31, 2014
Applicants:
Mehul D. Shroff, Austin, TX (US);
Douglas M Reber, Austin, TX (US);
Edward O. Travis, Austin, TX (US);
Inventors:
Mehul D. Shroff, Austin, TX (US);
Douglas M Reber, Austin, TX (US);
Edward O. Travis, Austin, TX (US);
Assignee:
Freescale Semiconductor, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 23/522 (2006.01); G06F 17/50 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G06F 17/5077 (2013.01); H01L 21/76877 (2013.01); H01L 23/53238 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.