The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Dec. 05, 2014
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823418 (2013.01); H01L 21/02362 (2013.01); H01L 21/3081 (2013.01); H01L 21/823814 (2013.01); H01L 27/088 (2013.01); H01L 29/41783 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01); H01L 29/66636 (2013.01);
Abstract
A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.